In recent years, in various electronic devices, spaces for installing electronic components have tended to be reduced. Thus, an electronic device sheet including a capacitor has a demand for a reduction in profile. For the reduction of an electronic device sheet in profile, it is effective to reduce the thicknesses of a dielectric layer. As one of the techniques therefor, there is a known method of manufacturing an electronic device sheet of a capacitor or the like by forming a thin dielectric layer on an electrode layer using a thin film forming technology such as a sputtering method. However, thinning a dielectric layer tends to lead to reductions in withstanding voltage and leakage properties of the dielectric layer. For this reason, techniques for improving the withstanding voltage and the leakage properties in accordance with thinning a dielectric layer are under study. For example, Patent Literature 1 discloses a technique that optimizes a material, a crystalline structure, and an orientation with respect to the surface of a substrate, of a dielectric layer in an electronic device sheet, so as to improve the leakage properties and the withstanding voltage of the dielectric layer.